74F823 Datasheet | Fairchild Semiconductor

74F823 9-Bit D-Type Flip-Flop April 1988 Revised August 1999 74F823 9-Bit D-Type Flip-Flop General Description The 74F823 is a 9-bit buffered register. It Features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. Features s 3-STATE outputs s Clock Enable and Clear Ordering Code: Order Number 74F823SC 74F823SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009596 .fairchildsemi. Unit Loading/Fan Out Pin Names D0- D8 OE CLR CP EN O0- O8 Description Data Inputs Output Enable Input Clear Clock Input Clock Enable 3-STATE Outputs U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 150/40 (33.3) Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 1.2 m A 20 µA/- 0.6 m A - 3 m A/24 m A (20 m A) Functional Description The 74F823 device consists of nine D-type edge-triggered flip-flops. It has 3-STATE true outputs and is organized in broadside pinning. The buffered Clock (CP) and buffered Output Enable (OE) are mon to all flip-flops. The flipflops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOWto-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. In addition to the Clock and Output Enable pins, the 74F823 has Clear (CLR) and Clock Enable (EN) pins. When the CLR is LOW and the OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flipflops. When EN is LOW, data on the...