74F899 Datasheet | Fairchild Semiconductor

Description The 74F899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability of 24 m A at the A-bus and 64 m A at the B-bus. The 74F899 Features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. Features s Latchable transceiver with output sink of 24 m A at the A-bus and 64 m A at the B-bus s Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A s Independent latch enables for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in systems applications in place of the 74F543 and 74F280 s May be used in system applications in place of the 74F657 and 74F373 (no need to change T/R to check parity) Ordering Code: Order Number 74F899SC 74F899QC Package Number M28B V28A Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for SOIC Pin Assignment for PCC Logic Symbol © 1999 Fairchild Semiconductor Corporation DS010195 .fairchildsemi. Input Loading/Fan-Out HIGH/LOW Pin Names Description U.L. HIGH/LOW A0- A7 B0- B7 APAR BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB Data Inputs/ Data Outputs Data Inputs/ Data Outputs A Bus Parity Input/Output B Bus Parity Input/Output Parity Select Input Output Enable Inputs Mode Select Input Latch Enable Inputs Error Signal Outputs 1.0/1.0 150/40 1.0/1.0 600/106.6 1.0/1.0 150/40 1.0/1.0 600/106.6 1.0/1.0...