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74ALS125 - Quad 3-STATE Buffer

Description

This device contains four independent gates each of which performs a non-inverting buffer function.

The outputs have the 3-STATE feature.

The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or rampdown.

Features

  • s Advanced low power oxide-isolated ion-implanted Schottky TTL process s Functional and pin compatible with the 74LS counterpart s Switching response specified into 500Ω and 50 pF load s Switching response specifications guaranteed over full temperature and VCC supply range s PNP input design reduces input loading s Low level.

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Full PDF Text Transcription

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DM74ALS125 Quad 3-STATE Buffer November 1989 Revised February 2000 DM74ALS125 Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or rampdown. This eliminates bus glitching problems that arise during power-up and power-down. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.
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