74F162A Datasheet | Fairchild Semiconductor

74F160A - 74F162A Synchronous Presettable BCD Decade Counter April 1988 Revised July 1999 74F160A - 74F162A Synchronous Presettable BCD Decade Counter General Description The 74F160A and 74F162A are high-speed synchronous decade counters operating in the BCD (8421) sequence. They are synchronously presettable for applications in programmable dividers. There are two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The F160A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The F162A has a Synchronous Reset input that overrides counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the clock. The F160A and F162A are high speed versions of the F160 and F162. Features s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 120 MHz Ordering Code: Order Number 74F160ASC 74F160ASJ 74F160APC 74F162ASC 74F162APC Package Number M16A M16D N16E M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F160A © 1999 Fairchild Semiconductor Corporation DS009485 .fairchildsemi. 74F160A - 74F162A Logic Symbols 74F160A IEEE/IEC 74F160A Unit Loading/Fan Out U.L. Pin Names CEP CET CP Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 50/33.3 50/33.3 Input IIH/IIL HIGH/LOW Output...