74LS241 Datasheet | Fairchild Semiconductor

DM74LS240 - DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver August 1986 Revised March 2000 DM74LS240 - DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 m V of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133Ω. Features s 3-STATE outputs drive bus lines directly s PNP inputs reduce DC loading on bus lines s Hysteresis at data inputs improves noise margins s Typical IOL (sink current) 24 m A s Typical IOH (source current) - 15 m A s Typical propagation delay times Inverting Noninverting 10.5 ns 12 ns s Typical enable/disable time 18 ns s Typical power dissipation (enabled) Inverting Noninverting 130 m W 135 m W Ordering Code: Order Number DM74LS240WM DM74LS240SJ DM74LS240N DM74LS241WM DM74LS241N Package Number M20B M20D N20A M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74LS240 DM74LS241 © 2000 Fairchild Semiconductor Corporation DS006411 .fairchildsemi. DM74LS240 - DM74LS241 Function Tables DM74LS240 Inputs G L L H A L H X Output Y H L Z G X X X H H L L = LOW Logic Level H = HIGH Logic Level X = Either LOW or HIGH Logic Level Z = High Impedance DM74LS241 Inputs G L L H X X X 1A L H X X X X 2A X X X L H X Outputs 1Y L H Z...