74LVT16646 Datasheet | Fairchild Semiconductor

Description The LVT16646 and LVTH16646 contains sixteen noninverting bidirectional registered bus transceivers providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The DIR inputs determine the direction of data flow through the device. The CPAB and CPBA inputs load data into the registers on the LOW-to-HIGH transition (see Functional Description ). The LVTH16646 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16646 and LVTH16646 are fabricated with an advanced Bi CMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16646) s Also available without bushold feature (74LVT16646) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink - 32 m A/+64 m A s Latch-up conforms to JEDEC JED78 s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number 74LVT16646MEA (Preliminary) 74LVT16646MTD (Preliminary) 74LVTH16646MEA 74LVTH16646MTD Package Number MS56A MTD56 MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the...