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74LVTH16240 Datasheet

Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

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74LVTH16240 pdf
March 1999
Revised March 1999
74LVT16240 • 74LVTH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16240 and LVTH16240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus-oriented
transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16240 and
LVTH16240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16240), also
available without bushold feature (74LVT16240).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 16240
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS012025.prf
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74LVTH16240 Datasheet

Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

No Preview Available !

74LVTH16240 pdf
Connection Diagram
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Inputs (Active Low)
Inputs
3-STATE Outputs
Truth Table
Inputs
OE1
I0–I3
LL
LH
HX
Inputs
OE2
I4–I7
LL
LH
HX
Inputs
OE3
I8–I11
LL
LH
HX
Inputs
OE4
L
L
H
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
I12–I15
L
H
X
Outputs
O0–O3
H
L
Z
Outputs
O4–O7
H
L
Z
Outputs
O8–O11
H
L
Z
Outputs
O12–O15
H
L
Z
Functional Description
The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble (4
bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted
together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nib-
ble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode,
but this does not interfere with entering new data into the inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2


Part Number 74LVTH16240
Description Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
Maker Fairchild Semiconductor
Total Page 6 Pages
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