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Fairchild Semiconductor Electronic Components Datasheet

74LVTH273 Datasheet

Low Voltage Octal D-Type Flip-Flop with Clear

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74LVTH273 pdf
July 1999
Revised July 1999
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
General Description
The LVTH273 is a high-speed, low-power positive-edge-
triggered octal D-type flip-flop featuring separate D-type
inputs for each flip-flop. A buffered Clock (CP) and Clear
(CLR) are common to all flip-flops.
The state of each D-type input, one setup time before the
positive clock transition, is transferred to the corresponding
flip-flop’s output.
The LVTH273 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH273 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold on the data inputs eliminate the need for
external pull-up resistors to hold unused inputs
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 273
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVTH273WM
74LVTH273SJ
74LVTH273MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS500100
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74LVTH273 Datasheet

Low Voltage Octal D-Type Flip-Flop with Clear

No Preview Available !

74LVTH273 pdf
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
CLR
O0–O7
Truth Table
Description
Data Inputs
Clock Pulse Input
Clear
Outputs
Inputs
Dn CP CLR
H H
L H
X H or L H
XXL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Oo = Previous Oo before HIGH-to-LOW of CP
Outputs
On
H
L
Oo
L
Functional Description
The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear
are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input sig-
nal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Part Number 74LVTH273
Description Low Voltage Octal D-Type Flip-Flop with Clear
Maker Fairchild Semiconductor
Total Page 6 Pages
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