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Fairchild Semiconductor Electronic Components Datasheet

74LVTH322374 Datasheet

Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25 Series Resistors in the Outputs (Preliminary)

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74LVTH322374 pdf
Preliminary
February 2001
Revised August 2001
74LVTH322374
Low Voltage 32-Bit D-Type Flip-Flop
with 3-STATE Outputs
and 25Series Resistors in the Outputs (Preliminary)
General Description
The LVTH322374 contains thirty-two non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 32-bit opera-
tion.
The LVTH322374 is designed with equivalent 25series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
The LVTH322374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH322374 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Power Down high impedance provides glitch-
free bus loading
s Outputs include equivalent series resistance of 25to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Order Number Package Number
Package Description
74LVTH322374GX
(Note 1)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [Tape and Reel]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500429
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74LVTH322374 Datasheet

Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25 Series Resistors in the Outputs (Preliminary)

No Preview Available !

74LVTH322374 pdf
Preliminary
Connection Diagram
Pin Descriptions for FBGA
Pin Names
OEn
CPn
I0–I31
O0–O31
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
FBGA Pin Assignments
(Top Thru View)
123456
A
O1
O0 OE1 CP1
I0
I1
B O3 O2 GND GND I2
I3
C
O5
O4 VCC1 VCC1
I4
I5
D O7 O6 GND GND I6
I7
E O9 O8 GND GND I8
I9
F O11 O10 VCC1 VCC1 I10 I11
G O13 O12 GND GND I12 I13
H
O14 O15 OE2 CP2
I15
I14
J
O17 O16 OE3 CP3
I16
I17
K O19 O18 GND GND I18 I19
L O21 O20 VCC2 VCC2 I20 I21
M O23 O22 GND GND I22 I23
N O25 O24 GND GND I24 I25
P O27 O26 VCC2 VCC2 I26 I27
R O29 O28 GND GND I28 I29
T
O30 O31 OE4 CP4
I31
I30
Truth Tables
Inputs
CP1
OE1
L
L
LL
XH
Inputs
CP3
OE3
L
L
LL
XH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
I0–I7
H
L
X
X
I16–I23
H
L
X
X
Outputs
O0–O7
H
L
Oo
Z
Outputs
O16–O23
H
L
Oo
Z
Inputs
CP2
OE2
I8–I15
L H
L L
LLX
XHX
Inputs
CP4
OE4
L
L
I24–I31
H
L
LLX
XHX
Z = HIGH Impedance
Oo = Previous Oo before HIGH-to-LOW of CP
Outputs
O8–O15
H
L
Oo
Z
Outputs
O24–O31
H
L
Oo
Z
Functional Description
The LVTH322374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be
shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all
flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi-
vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the
Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to
the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
www.fairchildsemi.com
2


Part Number 74LVTH322374
Description Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25 Series Resistors in the Outputs (Preliminary)
Maker Fairchild Semiconductor
Total Page 6 Pages
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