74VHC4046 Datasheet | Fairchild Semiconductor

.. 74VHC4046 CMOS Phase Lock Loop April 1994 Revised October 2003 74VHC4046 CMOS Phase Lock Loop General Description The VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase parator and VCO sections. This device contains a low power linear voltage controlled oscillator (VCO), a source follower, and three phase parators. The three phase parators have a mon signal input and a mon parator input. The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the phase parators with a small signal or directly coupled with standard input logic levels. This device is similar to the CD4046 except that the Zener diode of the metal gate CMOS device has been replaced with a third phase parator. Phase parator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintains a 90 phase shift between the VCO’s center frequency and the input signal (50% duty cycle input waveforms). This phase detector is more susceptible to locking onto harmonics of the input frequency than phase parator I, but provides better noise rejection. Phase parator III is an SR flip-flop gate. It can be used to provide the phase parator functions and is similar to the first parator in performance. Phase parator II is an edge sensitive digital sequential network. Two signal outputs are provided, a parator output and a phase pulse output. The parator output is a 3-STATE output that provides a signal that locks the VCO output signal to the input signal with 0 phase shift between them. This parator is more susceptible to noise throwing the loop out of lock, but is less likely to lock onto harmonics than the other two parators. In a typical application any one of the three parators feed an external filter network which in turn feeds the VCO input. This input is a very high impedance CMOS input...