s Contains six flip-flops with single-rail outputs s Buffered clock and direct clear inputs s Individual data input to each flip-flop s Applications include: Buffer/stora.

include: Buffer/storage registers Shift registers Pattern generators s Typical clock frequency 40 MHz s Typical power di.

These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input. Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positiv.

DM7417

DM74170

DM74173

DM74175

DM7410

DM74121

DM74121N

DM74122

DM74123

DM74125

DM74132

DM7414

DM74141