* complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the po
DM74ALS174 Datasheet (73.30 KB)
DM74ALS174
Fairchild Semiconductor
73.30 KB
Hex/quad d-type flip-flops.
DM74ALS174 DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear September 1986 Revised February 2000 DM74ALS174 DM74ALS175 Hex/Quad .
📁 Related Datasheet
DM74ALS175 Hex/Quad D-Type Flip-Flops (Fairchild Semiconductor)
DM74ALS1000A Quadruple 2-Input NAND Buffer (Fairchild Semiconductor)
DM74ALS1004 Hex Inverting Driver (Fairchild Semiconductor)
DM74ALS1005 Hex Inverting Driver (Fairchild Semiconductor)
DM74ALS1008A Quadruple 2-Input AND Buffer (Fairchild Semiconductor)
DM74ALS1011A Triple 3 Input AND Buffer (National)
DM74ALS1032A Quadruple 2-Input OR Buffer (Fairchild Semiconductor)
DM74ALS1034 Hex Non-Inverting Driver (Fairchild Semiconductor)
DM74ALS1035 Hex Non-Inverting Driver with Open Collector Outputs (Fairchild Semiconductor)
DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop (Fairchild Semiconductor)
