DM74ALS74A Datasheet | Fairchild Semiconductor

Description The DM74ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also plementary Q and Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. Features s Switching specifications at 50 p F s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin patible with Schottky and LS TTL counterpart s Improved AC performance over LS74 at approximately half the power Ordering Code: Order Number DM74ALS74AM DM74ALS74ASJ DM74ALS74AN Package Number Package Description M14A M14D N14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs PR L H L H H H CLR H L L H H H CLK X X X ↑ ↑ L D X X X H L X Q H L H (Note 1) H L Q0 Outputs Q L H H (Note 1) L H Q0 L = LOW State H = HIGH State X = Don't Care ↑ = Positive Edge Transition Q0 = Previous Condition of Q Note 1: This condition is nonstable; it will not persist when preset and clear inputs return to their inactive (HIGH) level. The output levels in this condition are not guaranteed to meet the VOH specification. © 2000 Fairchild Semiconductor Corporation DS006109 .fairchildsemi. Logic Diagram .fairchildsemi. DM74ALS...