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DM74LS175 - Hex/Quad D-Type Flip-Flops

Download the DM74LS175 datasheet PDF. This datasheet also covers the DM74LS174 variant, as both devices belong to the same hex/quad d-type flip-flops family and are provided as variant models within a single manufacturer datasheet.

Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic.

All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop.

Features

  • s DM74LS174 contains six flip-flops with single-rail outputs s DM74LS175 contains four flip-flops with double-rail outputs s Buffered clock and direct clear inputs s Individual data input to each flip-flop s.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM74LS174_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DM74LS175 Hex/Quad D Flip-Flops National Semiconductor
DM74LS173A 4-Bit D-Type Register National Semiconductor
DM74LS174 Hex/Quad D Flip-Flops National Semiconductor
DM74LS10 Triple 3-Input NAND Gates National Semiconductor
DM74LS107A Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops National Semiconductor

Other Datasheets by Fairchild (onsemi)

Part Number Description
DM74LS174 Hex/Quad D-Type Flip-Flops
DM74LS10 Triple 3-Input NAND Gate
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop
DM74LS11 Triple 3-Input AND Gate
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear August 1992 Revised April 2000 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.
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