Fairchild Semiconductor DM74LS93M
The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. The device should not be operated at these limits.| Part No. | DM74LS93M |
|---|---|
| Datasheet | DM74LS93M Download |
| Manufacturer |  Fairchild Semiconductor |
| Description | Decade and Binary Counters |
| Buy | Stock & Price |
GENERAL DESCRIPTION
Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the ’LS90 and divide-by-eight for the ’LS93. All of these counters have a gated zero reset and the LS90 also has gated set-to-nine inputs for use in BCD nine’s complement applications. To use their maximum count length (decade or four bit binary), the B input is connected to the QA output. A symmetrical divide-by-ten count can be obtained from the ’LS90 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.FEATURES
n Typical power dissipation 45 mW n Count frequency 42 MHz Connection Diagrams (Dual-In-Line Packages) DS006381-1 Order Number DM74LS90M or DM74LS90N See Package Number M14A or N14A DS006381-2 Order Number DM74LS93M or DM74LS93N See Package Number...
