DM74S182 Datasheet | Fairchild Semiconductor

DM74S182 Look-Ahead Carry Generator August 1986 Revised March 2000 DM74S182 Look-Ahead Carry Generator General Description These circuits are high-speed, look-ahead carry generators, capable of anticipating a carry across four binary adders or groups of adders. They are cascadable to perform full look-ahead across n-bit adders. Carry, generatecarry, and propagate-carry functions are provided as shown in the pin designation table. When used in conjunction with the 181 arithmetic logic unit, these generators provide high-speed carry look-ahead capability for any word length. Each DM74S182 generates the look-ahead (anticipated carry) across a group of four ALU’s and, in addition, other carry look-ahead circuits may be employed to anticipate carry across sections of four look-ahead packages up to n-bits. The method of cascading circuits to perform multi-level look-ahead is illustrated under typical application data. Carry input and output of the ALU’s are in their true form, and the carry propagate (P) and carry generate (G) are in negated form; therefore, the carry functions (inputs, out- puts, generate, and propagate) of the look-ahead generators are implemented in the patible forms for direct connection to the ALU. Reinterpretations of carry functions, as explained on the 181 data sheet are also applicable to and patible with the look-ahead generator. Positive logic equations for the DM74S182 are: Cn + x = G0 + P0 Cn Cn + y = G1 + P1 G0 + P1 P0 Cn Cn + z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn G = G3 (P3 + G2) (P3 + P2 + G1) (P3 + P2 + P1 + G0) P = P3 P2 P1 P0 Features s Typical propagation delay time 7 ns s Typical power dissipation 260 m W Ordering Code: Order Number Package Number Package Description DM74S182N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Pin Designations Designation G0, G1, G2, G3 P0, P1, P2, P3 Cn Cn + x, Cn + y, Cn + z G VCC GND Pin Nos. 3, 1, 14, 5 4, 2, 15, 6 13 12, 11,...