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Fairchild Semiconductor Electronic Components Datasheet

DM96S02 Datasheet

Dual Retriggerable Resettable Monostable Multivibrator

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January 1992
Revised June 1999
DM96S02
Dual Retriggerable Resettable Monostable Multivibrator
General Description
The DM96S02 is a dual retriggerable and resettable
monostable multivibrator. This one-shot provides excep-
tionally wide delay range, pulse width stability, predictable
accuracy and immunity to noise. The pulse width is set by
an external resistor and capacitor. Resistor values up to 2.0
Mfor the DM96S02 reduce required capacitor values.
Hysteresis is provided on the positive trigger input of the
DM96S02 for increased noise immunity.
Order Code:
Order Number Package Number
Package Description
DM96S02M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM96S02N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
VCC = Pin 16
GND = Pin 8
Pin Descriptions
Pin Names
Description
I0 Trigger Input (Active Falling Edge)
I1 Schmitt Trigger Input (Active Rising-Edge)
CD
Q1 - 2
Direct Clear Input (Active-LOW)
True Pulse Output
Q1 - 2
Complementary Pulse Output
CX1, 2
RX1,2
External Capacitor Connection
External Resistor Connection
Triggering Truth Table
Pin Number
5(11)
4(12)
3(13)
HL
L
H
H LH H
XXL
H = HIGH Voltage Level VIH
L = LOW Voltage Level VIL
X = Immaterial (either H or L)
H L = HIGH-to-LOW Voltage Level transition
L H = LOW-to-HIGH Voltage Level transition
Operation
Trigger
Trigger
Reset
© 1999 Fairchild Semiconductor Corporation DS009810.prf
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

DM96S02 Datasheet

Dual Retriggerable Resettable Monostable Multivibrator

No Preview Available !

Functional Description
The 96S02 dual retriggerable resettable monostable multi-
vibrator has tow DC coupled trigger inputs per function,
one active LOW (I0) and one active HIGH (I1). The I1 input
utilizes an internal Schmitt trigger with hysteresis of 0.3V to
provide increased noise immunity. The use of active HIGH
and LOW inputs allows wither rising or falling edge trigger-
ing and optional non-retriggerable operation. The inputs
are DC coupled making triggering independent of input
transition times. When input conditions for triggering are
met the Q output goes HIGH and the external capacitor is
rapidly discharged and then allowed to recharge. An input
Block Diagram
trigger which occurs during the timing cycle will retrigger
the circuit and result in Q remaining HIGH. The output
pulse may be terminated (Q to the LOW state) at any time
by setting the Direct Clear input LOW. Retriggering may be
inhibited by tying the Q output to I0 or the Q output to I1.
Differential sensing techniques are used to obtain excellent
stability over temperature and power supply variations and
a feedback Darlington capacitor discharge circuit mini-
mizes pulse width variation from unit to unit. Schottky TTL
output stages provide high switching speeds and output
compatibility with all TTL logic families.
www.fairchildsemi.com
2


Part Number DM96S02
Description Dual Retriggerable Resettable Monostable Multivibrator
Maker Fairchild Semiconductor
Total Page 7 Pages
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