Datasheet Details
| Part number | 56F8014 |
|---|---|
| Manufacturer | Freescale Semiconductor (now NXP Semiconductors) |
| File Size | 966.32 KB |
| Description | 16-bit Digital Signal Controllers |
| Datasheet |
 56F8014 Datasheet
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| Part number | 56F8014 |
|---|---|
| Manufacturer | Freescale Semiconductor (now NXP Semiconductors) |
| File Size | 966.32 KB |
| Description | 16-bit Digital Signal Controllers |
| Datasheet |
56F8014 Datasheet
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of Change Rev 2 Rev 3 Please see http://www.freescale.com for the most current Data Sheet revision.
56F8014 Technical Data, Rev.
3 2 Freescale Semiconductor Preliminary www.DataSheet4U.com 56F8014 General Description • Up to 32 MIPS at 32MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 16KB Program Flash • 4KB Unified Data/Program RAM • One 5-channel PWM module • Two 4-channel 12-bit ADCs • One Serial Communication Interface (SCI) with LIN slave functionality • One Serial Peripheral Interface (SPI) • One 16-bit Quad Timer • One Inter-Integrated Circuit (I2C) Port • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • Integrated Power-On Reset and Low-Voltage Interrupt Module • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 26 GPIO lines • 32-pin LQFP Package RESET 4 VCAP VDD VSS_IO 2 VDDA VSSA 5 PWM Outputs PWM or Timer Port or GPIOA Program Controller and Hardware Looping Unit JTAG/EOnCE Port or GPIOD Digital Reg Analog Reg 16-Bit 56800E Core Low-Voltage Supervisor Bit Manipulation Unit Address Generation Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators 4 AD0 4 ADC or GPIOC PAB PDB CDBR CDBW Memory Program Memory 8K x 16 Flash Unified Data / Program RAM 4KB XDB2 XAB1 XA
www.DataSheet4U.com 56F8014 Data Sheet Preliminary Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8014 Rev.
3 9/2005 freescale.com www.DataSheet4U.com Document Revision History Version History Rev 0 Rev 1 Initial release Updates to Part 10, Specifications, Table 10-1, added maximum clamp current , per pin Table 10-11, clarified variation over temperature table and graph Table 10-15, added LIN slave timing Added alternate pins to Figure 11-1 and Table 11-1.
Corrected bit selects in Timer Channel 3 Input (TC3_INP) bit 9 , Section 6.3.1.7, clarified Section 1.4.
| Part Number | Description |
|---|---|
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