Datasheet4U Logo Datasheet4U.com

56F805 - 16-bit Digital Signal Controllers

Description

Added revision history.

Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unifi

Features

  • 1.1.1 Processing Core.
  • Efficient 16-bit 56800 family processor engine with dual Harvard architecture.
  • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency.
  • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC).
  • Two 36-bit accumulators, including extension bits.
  • 16-bit bidirectional barrel shifter.
  • Parallel instruction set with unique processor addressing modes.
  • Hardware DO and REP loops.
  • Thre.

📥 Download Datasheet

📁 Similar Datasheet

  • 56F805 - 16-bit Hybrid Controller (Motorola)
  • 56F801 - 16-bit Hybrid Controller (Motorola)
  • 56F8011 - (56F8011 / 56F8013) 16-Bit Digital Signal Controller (Motorola Semiconductor)
  • 56F8013 - (56F8011 / 56F8013) 16-Bit Digital Signal Controller (Motorola Semiconductor)
  • 56F802 - 56F802 16-bit Hybrid Controller (Motorola)
  • 56F8023 - 16-bit Digital Signal Controllers (Motorola Semiconductor)
  • 56F8025 - 16-bit Digital Signal Controllers (Motorola Semiconductor)
  • 56F803 - 16-bit Hybrid Controller (Motorola)
  • 56F8033 - 16-bit Digital Signal Controllers (Motorola Semiconductor)
  • 56F8035 - 16-bit Digital Signal Controllers (Motorola Semiconductor)
Other Datasheets by Freescale Semiconductor
  • 56F800 - 16-bit Digital Signal Controllers
  • 56F801 - 16-bit Digital Signal Controllers
  • 56F8013 - 16-bit Digital Signal Controllers
  • 56F8014 - 16-bit Digital Signal Controllers
  • 56F802 - 16-bit Digital Signal Controllers
  • 56F8023 - 16-bit Digital Signal Controllers
  • 56F8025 - Digital Signal Controller Product Brief
  • 56F8027 - 16-bit Digital Signal Controllers

Full PDF Text Transcription

Click to expand full text
56F805 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F805 Rev. 16 09/2007 freescale.com Version History Rev. 16 Document Revision History Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.” 56F805 General Description • Up to 40 MIPS at 80MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Hardware DO and REP loops • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • 31.
Published: |