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56F8156 - (56F8156 / 56F8356) 16-bit Digital Signal Controllers

General Description

in Table 2-2, added note to Table 10-7 and clarified Section 12.3.

Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering.

Key Features

  • in italics are NOT available in the 56F8156 device.
  • Up to 60 MIPS at 60MHz core frequency.
  • DSP and MCU functionality in a unified, C-efficient architecture.
  • Access up to 1MB of off-chip program and data memory.
  • Chip Select Logic for glueless interface to ROM and SRAM.
  • 256KB of Program Flash.
  • 4KB of Program RAM.
  • 8KB of Data Flash.
  • 16KB of Data RAM.
  • 16KB of Boot Flash.
  • Up to two 6-channel PWM modules.

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Full PDF Text Transcription for 56F8156 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 56F8156. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com 56F8356/56F8156 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.com Document Revis...

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nal Controllers MC56F8356 Rev. 13 01/2007 freescale.com Document Revision History Version History Rev 1.0 Rev 2.0 Initial Public Release Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added “Typical Min” values to Table 10-18. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing Table 10-18, ADC Parameters Table 10-24, and IO Loading Coefficients at 10MHz Table 10-25. Added Part 4.8, added the word “access” to FM Error Interrupt in Table 4-5, documenting o

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