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MC100ES6017 - 3.3V ECL/PECL Quad Differential Receiver

General Description

© Freescale Semiconductor, Inc., 2005.

All rights reserved.

Table 1.

Key Features

  • High bandwidth output transitions LVPECL operating range: VCC = 3.0 V to 3.6 V Internal input pulldown resistors on D inputs, pullup and pulldown resistors on D inputs 20 lead SOIC package Ambient temperature range -40°C to +85°C 20-lead Pb-free package available MC100ES6017 ECL/PECL QUAD.

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Other Datasheets by Freescale Semiconductor (now NXP Semiconductors)

Part Number Description
MC100ES6014 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6039 3.3V ECL/PECL/HSTL/LVDS Generation Chip
MC100ES6056 2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
MC100ES60T22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100ES6139 Clock Generation Chip

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Freescale Semiconductor Technical Data Document Number: MC100ES6017 Rev 2, 09/2005 www.DataSheet4U.com 3.3 V ECL/PECL Quad Differential Receiver The MC100ES6017 is a 3.3 V ECL/PECL quad differential receiver. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • • • • • • High bandwidth output transitions LVPECL operating range: VCC = 3.0 V to 3.