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MC100ES6039 Datasheet 3.3V ECL/PECL/HSTL/LVDS Generation Chip

Manufacturer: Freescale Semiconductor (now NXP Semiconductors)

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Overview

Freescale Semiconductor Technical Data MC100ES6039 Rev 2, 06/2005 www.DataSheet4U.com 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6 Clock Generation Chip The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications.

The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.

The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals.

Key Features

  • Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE =.
  • 3.135 V to.
  • 3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible 20-Lead Pb-Free Package Available MC100ES603.

More Datasheets from Freescale Semiconductor (now NXP Semiconductors)

Part Number Description
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