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MC100ES6039 3.3V ECL/PECL/HSTL/LVDS Generation Chip

MC100ES6039 Description

Freescale Semiconductor Technical Data MC100ES6039 Rev 2, 06/2005 www.DataSheet4U.com 3.3 V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6 Clock Generation Chip The .
Pin CLK(1), CLK(1) EN(1) MR(1) www.

MC100ES6039 Features

* Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE =
* 3.135 V to

MC100ES6039 Applications

* The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal

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Datasheet Details

Part number
MC100ES6039
Manufacturer
Freescale Semiconductor
File Size
260.61 KB
Datasheet
MC100ES6039_FreescaleSemiconductor.pdf
Description
3.3V ECL/PECL/HSTL/LVDS Generation Chip

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📌 All Tags

3.3V ECL PECL HSTL LVDS Generation Chip Freescale Semiconductor
Freescale Semiconductor MC100ES6039-like datasheet