MC100ES6039 - 3.3V ECL/PECL/HSTL/LVDS Generation Chip

Freescale Semiconductor

The MC100ES6039 by Freescale Semiconductor is a 3.3V ECL/PECL/HSTL/LVDS Generation Chip. Below is the official datasheet preview.

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MC100ES6039 3.3V ECL/PECL/HSTL/LVDS Generation Chip by Freescale Semiconductor - Datasheet Preview — Official preview page of the **MC100ES6039** 3.3V ECL/PECL/HSTL/LVDS Generation Chip datasheet (Freescale Semiconductor).

Datasheet Details

Part number	MC100ES6039
Manufacturer	Freescale Semiconductor
File Size	260.61 KB
Description	3.3V ECL/PECL/HSTL/LVDS Generation Chip
Datasheet	MC100ES6039_FreescaleSemiconductor.pdf
Additional preview pages of the MC100ES6039 datasheet.

MC100ES6039 Product details

Description

Pin CLK(1), CLK(1) EN(1) MR(1) www.DataSheet4U.com Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Freq.Select Input ÷2/4 ECL Freq.Select Input ÷4/6 ECL Positive Supply ECL Negative Supply No Connect 1 VCC 2 EN 3 DIVSELb 4 CLK 5 CLK 6 VBB 7 MR 8 VCC 9 NC 10 DIVSELa VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa(1) DIVSELb(1) VCC VEE NC Warning: All VCC and VEE pins must be externally connected to Power

Features

Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE =.
3.135 V to.
3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible 20-Lead Pb-Free Package Available MC100ES603.

📁 MC100ES6039 Similar Datasheet

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Other Datasheets by Freescale Semiconductor

MC100ES6014 - 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
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MC100ES6139 - Clock Generation Chip
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Published: Feb 24, 2010 |