MC908QY2 Key Features
- Added 8-pin dual flat no lead (DFN) packages to features list. Figure 1-2. MCU Pin Assignments
- Figure updated to include DFN packages. Figure 2-1. Memory Map
- Clarified illegal address and unimplemented memory
- Corrected bit definitions for Port A Data Register (PTA) and Data Direction Register A (DDRA). Table 13-3. Interrupt Sou
- Corrected vector addresses for keyboard interrupt and ADC conversion plete interrupt. Chapter 13 System Integration Modu
- Removed reference to break status register as it is duplicated in break module. 11.3.1 Internal Oscillator and 11.3.1.1
- Clarified oscillator trim option ordering information and what to expect with untrimmed device. Figure 11-5. Oscillator
- Bit 1 designation corrected. Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage)
- Diagram updated for clarity. 0.1 Figure 12-1. I/O Port Register Summary
- Corrected bit definitions for PTA7, DDRA7, and DDRA6. Figure 12-2. Port A Data Register (PTA)