Description
of Changes
5/21/2010 Initial public release.10/26/2010
Updated the block diagram.Corrected the CRCCTRL register, IRTC_TAMPER_SCR register, IRTC_STDBY_RAM register, changed the PCNT_PWM_CH1_VAL and PCNT_PWM_CH2_VAL to PCNT_PWM_CH0_VAL and PCNT_PWM_CH1_VAL in the Table 4-3; corrected PRACMPxC0 register in the Table 4-5. Updated Figure 4-2. Updated Table 5-2 for FTM vectors.Updated Table 17-1. Updated the Chapter 20, “Programmable Cyclic Redundancy Check (PCRCV1)”.Updated the Chapter 16, “In
Features
- 8-Bit HCS08 Central Processor Unit (CPU).
- New version of S08 core with same performance as traditional S08 and lower power.
- Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10MHz CPU at 3.6 V to 1.8 V, across temperature range of.
- 40 C to 85 C.
- HC08 instruction set with added BGND instruction.
- Support for up to 48 interrupt/reset sources. On-Chip Memory.
- Flash read/program/erase over full operating voltage and temperature.
- Random-acce.