MC9S12KC128 Datasheet, Freescale Semiconductor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Modes of Operation . . . . . . . . . . . . . . . . .

of Changes Change load cap value on VDD and VDDPLL. Correct expanded bus timing from 20MHz to 25 MHz. Move ATD interrupt vector from $ffd0 to $ffd2. Change PWeh and tDSW parameter in external bus timing. Expand to a K-Family SoC Guide and include 9S1.