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Freescale Semiconductor Electronic Components Datasheet

MCF5480 Datasheet

Microprocessor

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Freescale Semiconductor
Data Sheet
Document Number: MCF5485EC
Rev. 4, 12/2007
MCF548x ColdFire®
Microprocessor
Supports MCF5480, MCF5481,
MCF5482, MCF5483, MCF5484, and
MCF5485
MCF548x
TEPBGA–388
27 mm x 27 mm
Features list:
• ColdFire V4e Core
– Limited superscalar V4 ColdFire processor core
– Up to 200MHz peak internal core frequency (308 MIPS
[Dhrystone 2.1] @ 200 MHz)
– Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
– Memory Management Unit (MMU)
– Separate, 32-entry, fully-associative instruction and
data translation lookahead buffers
– Floating point unit (FPU)
– Double-precision conforms to IEE-754 standard
– Eight floating point registers
• Internal master bus (XLB) arbiter
– High performance split address and data transactions
– Support for various parking modes
• 32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
– 66–133 MHz operation
– Supports DDR and SDR DRAM
– Built-in initialization and refresh
– Up to four chip selects enabling up to one GB of external
memory
• Version 2.2 peripheral component interconnect (PCI) bus
– 32-bit target and initiator operation
– Support for up to five external PCI masters
– 33–66 MHz operation with PCI bus to XLB divider
ratios of 1:1, 1:2, and 1:4
• Flexible multi-function external bus (FlexBus)
– Provides a glueless interface to boot flash/ROM,
SRAM, and peripheral devices
– Up to six chip selects
– 33 – 66 MHz operation
• Communications I/O subsystem
– Intelligent 16 channel DMA controller
– Up to two 10/100 Mbps fast Ethernet controllers (FECs)
each with separate 2-Kbyte receive and transmit FIFOs
– Universal serial bus (USB) version 2.0 device controller
– Support for one control and six programmable
endpoints, interrupt, bulk, or isochronous
– 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte
of endpoint descriptor RAM
– Integrated physical layer interface
– Up to four programmable serial controllers (PSCs) each
with separate 512-byte receive and transmit FIFOs for
UART, USART, modem, codec, and IrDA 1.1 interfaces
– I2C peripheral interface
– Two FlexCAN controller area network 2.0B controllers
each with 16 message buffers
– DMA Serial Peripheral Interface (DSPI)
• Optional Cryptography accelerator module
– Execution units for:
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random Number Generator
• 32-Kbyte system SRAM
– Arbitration mechanism shares bandwidth between
internal bus masters
• System integration unit (SIU)
– Interrupt controller
– Watchdog timer
– Two 32-bit slice timers alarm and interrupt generation
– Up to four 32-bit general-purpose timers, compare, and
PWM capability
– GPIO ports multiplexed with peripheral pins
• Debug and test features
– ColdFire background debug mode (BDM) port
– JTAG/ IEEE 1149.1 test access port
• PLL and clock generator
– 30 to 66.67 MHz input frequency range
• Operating Voltages
– 1.5V internal logic
– 2.5V DDR SDRAM bus I/O
– 3.3V PCI, FlexBus, and all other I/O
• Estimated power consumption
– Less than 1.5W (388 PBGA)
© Freescale Semiconductor, Inc., 2007. All rights reserved.


Freescale Semiconductor Electronic Components Datasheet

MCF5480 Datasheet

Microprocessor

No Preview Available !

Table of Contents
1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .6
4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Supply Voltage Sequencing and Separation Cautions . .6
4.3 General USB Layout Guidelines . . . . . . . . . . . . . . . . . . .8
4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5 Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10
6 PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12
8 FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13
9 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
9.1 SDR SDRAM AC Timing Characteristics . . . . . . . . . . .15
9.2 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18
10 PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
11 Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . .22
11.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .22
11.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .23
11.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24
11.4 MII Serial Management Channel Timing (MDIO,MDC).24
12 General Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . .25
13 I2C Input/Output Timing Specifications. . . . . . . . . . . . . . . . . .25
14 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . .26
15 DSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .29
16 Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . .29
17 Case Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
18 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
List of Figures
Figure 1. MCF548X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. System PLL VDD Power Filter . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Supply Voltage Sequencing and Separation Cautions . 7
Figure 4. Preferred VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Alternate VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 6. USB VDD Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. USBRBIAS Connection. . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 11
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios . . . . . . . 11
Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.SDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15.DDR Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 18
Figure 16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18.PCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19.MII Receive Signal Timing Diagram. . . . . . . . . . . . . . 23
Figure 20.MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 23
Figure 21.MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 24
Figure 22.MII Serial Management Channel TIming Diagram. . . 24
Figure 23.I2C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 26
Figure 24.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 25.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . 27
Figure 26.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . 27
Figure 27.TRST Timing Debug AC Timing Specifications . . . . . 27
Figure 28.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . . 28
Figure 29.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 28
Figure 30.DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 31.388-pin BGA Case Outline. . . . . . . . . . . . . . . . . . . . . 31
List of Tables
Table 1. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . 5
Table 5. USB Filter Circuit Values . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. I/O Driver Capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Clock Timing Specifications. . . . . . . . . . . . . . . . . . . . . 11
Table 8. MCF548x Divide Ratio Encodings. . . . . . . . . . . . . . . . 11
Table 9. Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . 12
Table 10.FlexBus AC Timing Specifications. . . . . . . . . . . . . . . . 13
Table 11.SDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 16
Table 12.DDR Clock Crossover Specifications . . . . . . . . . . . . . 18
Table 13.DDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 18
Table 14.PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 21
Table 15.MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . 23
Table 16.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 23
Table 17.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 24
Table 18.MII Serial Management Channel Signal Timing . . . . . 24
Table 19.General AC Timing Specifications . . . . . . . . . . . . . . . . 25
Table 20.I2C Input Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. I2C Output Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 26
Table 23.Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 28
Table 24.DSPI Modules AC Timing Specifications. . . . . . . . . . . 29
Table 25.Timer Module AC Timing Specifications . . . . . . . . . . . 29
MCF548x ColdFire® Microprocessor, Rev. 4
2 Freescale Semiconductor


Part Number MCF5480
Description Microprocessor
Maker Freescale Semiconductor
Total Page 30 Pages
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