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MMC2001 - M-CORE Reference Manual

General Description

2-10 2.8.4 Bus Operation 2-11 2.8.5 Processor Instruction/Data Transfers 2-13 2.8.6 Bus Exception Cycles 2-14 SECTION 3 SYSTEM MEMORY MAP 3.1 Overview 3-1 3.2 Peripheral Module Address Allocation 3-1 3.3 Peripheral Module Interface Operation 3-2 3.4 Peripheral Module Address Assignment 3-2 SEC

Key Features

  • 2-2 2.3 Microarchitecture Summary 2-2 2.4 Programming Model 2-3 2.5 Data Format Summary 2-5 2.6 Operand Addressing Capabilities 2-6 2.7 Instruction Set Overview 2-6 2.8 M.
  • CORE Bus Interface 2-8 2.8.1 Bus Characteristics 2-8 2.8.2 Bus Signals 2-9 2.8.3 Signal.

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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. M•CORE™ MMC2001 Reference Manual Revision 1.1 Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.