MPC5606S Datasheet | Freescale Semiconductor

Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5606S Rev. 8, 11/2011 MPC5606S Microcontroller Data Sheet - Single issue, 32-bit Power Architecture Book E pliant CPU core plex (e200z0h) - patible with classic Power PC instruction set - Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional Book E pliant code - On-chip ECC flash memory with flash controller - Up to 1 MB primary flash- two 512 KB modules with prefetch buffer and 128-bit data access port - 64 KB data flash- separate 4  16 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port - Up to 48 KB on-chip ECC SRAM with SRAM controller - Up to 160 KB on-chip non-ECC graphics SRAM with SRAM controller - Memory Protection Unit (MPU) with up to 12 region descriptors and 32-byte region granularity to provide basic memory access permission - Interrupt Controller (INTC) with up to 127 peripheral interrupt sources and eight software interrupts - 2 Frequency-Modulated Phase-Locked Loops (FMPLLs) - Primary FMPLL provides a 64 MHz system clock - Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to e MIOS modules and as alternate clock to the DCU for pixel clock generation - Crossbar switch architecture enables concurrent access of peripherals, flash memory, or RAM from multiple bus masters (AMBA 2.0 v6 AHB) - 16-channel Enhanced Direct Memory Access controller (e DMA) with multiple transfer request sources using a DMA channel multiplexer - Boot Assist Module (BAM) supports internal flash programming via a serial link (Flex CAN or LINFlex) - Display Control Unit to drive TFT LCD displays LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) - Includes processing of up to four planes that can be blended together - Offers a direct unbuffered hardware...