MBL8089-2 Datasheet | Fujitsu Semiconductor Limited

MBL 8089 MBL 8089-2 April 1985 Edition 3.0 NMOS 8 & 16-BIT I/O PROCESSOR The Fujitsu MB L 8089 is a revolutionary concept in microproce- ssor input/output processing. Packaged in a 40-pin DIP package. MBL 8089 is a high performance processor implemented in N-channel, depletion load silicon gate technology (NMOS). The MBL 8089's instruction set and capabilities are optimized for high speed, flexible and efficient I/O handling. It allows easy interface of Fujitsu's 16-bit MBL 8086 and 8-bit MBL 8088 microprocessors with 8- and 16-bit peripherals. In the REMOTE configuration, MBL 8089 bus is user definable allowing it to be patible with any8/16-bit Fujitsu microprocessor, interfacing easily to the Fujitsu multiprocessor system bus standard MULTIBUS- . The MBL 8089 performs the function of an intelligent DMA controller for the MBL 8086,88 family and with its processing power, can remove I/O overhead from the MBL 8086 or MBL 8088. It may operate pletely in parallel with a CPU, giving dramatically improved performance in I/O intensive applications. MBL 8089 provides two I/O channels, each supporting a transfer rate up to 1.25 Mbyte/sec (2.00 Mbyte/sec) at the standard clock frequency of 5 MHz(8 MHz). Memory based munication between the l OP and CPU enhances system flexibility and encourages software modularity, yielding more reliable, easier to develop systems. - High Speed DMA Capabilities Including I/O to Memory, Memory to I/O, Memory to Memory, and I/O to I/O - MBl8086, MBl 8088 patible: Removes I/O Overhead from CPU in i APX 86/11 or 88/11 Configuration - Allows Mixed Interface of 8- & 16-Bit Peripherals, to 8- & 16-Bit Processor Busses - 1 Mbyte Addressability - Memory Based munication with CPU - Supports l OCAL or REMOTE I/O Processing - Flexible, Intelligent DMA Functions Including Translation, Search, Word Assembly/Disassembly - MUl TIBUS- patible System Interface - Two Clock Rates: 5 MHz for MBl 8089 8 MHz for MBl 8089-2 - 40-pin Ceramic DIP...