MBL8259A-2 Datasheet | Fujitsu Semiconductor Limited

MBl8259A MBl8259A-2 NMOS PROGRAMMABLE INTERRUPT CONTROLLER July 1986 Edition 2.2 The MBL8259A Programmable Interupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single +5V supply. Circuitry is static, requiring no clock input. The MBL8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimizatic for a variety of sy;tem requirements. - MBL SOS6, MBL SOSS patible - MCS-SO- , MCS-S5- patible - Eight-Level Priority Controller - Expandable to 64 Levels - Programmable Interrupt Modes - Individual Request Mask Capability - Single + 5V Supply (No Clocks) - Two Package Options: -2S-Pin Ceramic DIP (Suffix: -C) -2S-Pin Plastic DIP (Suffix: -P) Fig. 1 - BLOCK DIAGRAM Fig. 2 - PIN CONFIGURATION DATA BUS BUFFER CONTROL LOGIC READ/ WAITE LOGIC AO 05------' CAS 0 CAS 1 CASCADE BUFFER! PARATOR INTERNAL BUS IRO IR1 IR2 IR3 IR4 IR5 IR6 , -_ _.--~ IR7 - Trade Mark of Intel Corporation Portions Reprinted by permission of Intel Corporation © Intel Corporation, 1980 ,-272 IR7 IR6 IR5...