Download the MBM29DL400TC-55 datasheet PDF.
This datasheet also covers the MBM29DL400TC variant, as both devices belong to the same 4m (512k x 8/256k x 16) bit family and are provided as variant models within a single manufacturer datasheet.
Key Features
Single 3.0 V read, program, and erase Minimizes system level power requirements.
Simultaneous operations Read-while-Erase or Read-while-Program.
Compatible with JEDEC-standard commands Uses same software commands as E2PROMs.
Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV400TC/BC) 48-pin TSOP(I) (Package suffix: PFTN.
Note: The manufacturer provides a single datasheet file (MBM29DL400TC_FujitsuMediaDevices.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for MBM29DL400TC-55 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
MBM29DL400TC-55. For precise diagrams, and layout, please refer to the original PDF.
FUJITSU SEMICONDUCTOR DATA SHEET DS05-20866-2E FLASH MEMORY CMOS 4M (512K × 8/256K × 16) BIT MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12 s FEATURES • Single 3...
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400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12 s FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Simultaneous operations Read-while-Erase or Read-while-Program • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV400TC/BC) 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) • Minimum 100,000 program/erase cycles • High performance 55 ns maximum access time • Sector erase architecture Two 16K byte, four 8K bytes, two 32K byte, and six 64K b
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MBM29DL400TC-55 Datasheet
