Download the MBM29F002TC-55 datasheet PDF.
This datasheet also covers the MBM29F002TC variant, as both devices belong to the same 2m (256k x 8) bit flash memory family and are provided as variant models within a single manufacturer datasheet.
Key Features
Single 5.0 V read, write, and erase Minimizes system level power requirements.
Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection.
32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix: PD).
Note: The manufacturer provides a single datasheet file (MBM29F002TC_FujitsuMediaDevices.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for MBM29F002TC-55 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
MBM29F002TC-55. For precise diagrams, and layout, please refer to the original PDF.
FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 2M (256K × 8) BIT DS05-20868-3E MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90 s FEATURES • Single 5.0 V read, write, an...
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0/-90/MBM29F002BC-55/-70/-90 s FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection • 32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix: PD) • Minimum 100,000 write/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes Any combination of sectors can be erased.
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MBM29F002TC-55 Datasheet
