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CA91 - CMOS AccelArray

Description

AccelArrayTM

is a new structured ASIC family, offering short development time, and low development cost with pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers.

Features

  • High-speed, large scale ASIC produced in short development time: TAT = One third compared with Standard Cell ASICs (target value).
  • Uses an architecture that simplifies physical design tasks.
  • Pre-designed common masters with IR-drop free.
  • Pre-designed test circuit insertion to reduce test synthesis tasks.
  • Uses a dedicated timing-driven layout tool to reduce development time.
  • Signal Integrity Free (pre-designed main clock trees without de.

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Other Datasheets by Fujitsu Media Devices

    Full PDF Text Transcription

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    FUJITSU SEMICONDUCTOR DATA SHEET DS06-10801-4E Semicustom CMOS AccelArrayTM CA91 Series ■ DESCRIPTION AccelArrayTM* is a new structured ASIC family, offering short development time, and low development cost with pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers. By using 0.11 µm CMOS process technology, the devices can support 6 million logic gates, 4.55 Mbits SRAM and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681 pins) packages are available. * : AccelArrayTM is a trademark of Fujitsu Limited.
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