CS101
Overview
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power consumption and higher speed. The leakage current of the transistors is the minimum level in the industry.
- Technology : 90 nm Si gate CMOS 7- to 10-metal layers. Low-K (low permittivity) material is used for all dielectric inter-layers. Three different types of core transistors (low leak, standard, and high speed) can be used on the same chip. The design rules comply with industry standard processes. Power supply voltage : +1.2 V ± 0.1 V (standard) Operation junction temperature : - 40 °C to + 125 °C (standard) Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1) Gate power consumption : Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1) High level of integration : Up to 91 million gates Reduced chip sized realized by I/O with pad. Support for a wide range of cell sets (from low power versions to ultra high speed versions). Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incorporated. Compiled cell (RAM, ROM, others) Support for ultra high speed (up to 10 Gbps) interface macros. Special interfaces (LVDS, SSTL2, etc.) Supports use of industry standard libraries (.LIB). Uses industry standard tools and supports the optimum tools for the applicatio
