MB90V595G Datasheet | Fujitsu Semiconductor Limited

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13705-3E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90595/595G Series .. MB90598/F598/F598G/V595/V595G s DESCRIPTION The MB90595/595G series with FULL-CAN- 1 interface and FLASH ROM is especially designed for automotive and industrial applications. Its main Features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC- 2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90595/595G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output pare (OCU)) and stepping motor controller. - 1: Controller Area Network (CAN) - License of Robert Bosch Gmb H - 2: F2MC stands for FUJITSU Flexible Microcontroller. s Features - Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) (Continued) s PACKAGE 100-pin Plastic QFP (FPT-100P-M06) MB90595/595G Series (Continued) - Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator - Instruction set designed for high level language (C language)...