* FR81S CPU Core
32-bit RISC, load/store architecture, 5-stage pipeline Maximum operating frequency:
MB91F52xR/MB91F52xU(LQFP): 80 MHz (Source oscillation = 4.0 M.
Memory-to-memory transfer instruction Bit processing instruction Barrel shift instruction etc. High-level langua.
of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committ.
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