MB93423 Overview
Description
This specifications describe the implementation of the MB93423, incorporating a processor core (FR403-SoC) designed for embedded applications, which is based on a VLIW (Very Long Instruction Word) architecture (the FR-V architecture). This processor can issue the integer operation instruction, media instruction, and branch instruction, up to two instructions, in units called the “VLIW instruction” on a cycle-by-cycle basis.
Key Features
- 2-way 240 MHz or 266 MHz VLIW Processor Core
- Instruction cache : 8 Kbyte (2way) , line size 32 byte
- Data cache : 8 Kbyte (2way) , line size 32 byte
