MB93423
Description
This specifications describe the implementation of the MB93423, incorporating a processor core (FR403-SoC) designed for embedded applications, which is based on a VLIW (Very Long Instruction Word) architecture (the FR-V architecture) . This processor can issue the integer operation instruction, media instruction, and branch instruction, up to two instructions, in units called the “VLIW instruction” on a cycle-by-cycle basis.
Key Features
- 2-way 240 MHz or 266 MHz VLIW Processor Core
- Peak Performance 480 MIPS (Integer operation performance) at 240 MHz 1920 MOPS + 240 MIPS (media operation performance) at 240 MHz 532 MIPS (Integer operation performance) at 266 MHz 2128 MOPS + 266 MIPS (media operation performance) at 266 MHz
- 64 32-bit registers (32GR + 32FR) Cache
- Instruction cache : 8 Kbyte (2way) , line size 32 byte
- Data cache : 8 Kbyte (2way) , line size 32 byte
- Cache line
