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GS81302Q19GE Datasheet Preview

GS81302Q19GE Datasheet

144Mb SigmaQuad-II+ Burst of 2 SRAM

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GS81302Q07/10/19/37E-318/300/250/200
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaQuad-II+TM
Burst of 2 SRAM
318 MHz–200 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• 2.0 clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GS81302Q07/10/19/37E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302Q07/10/19/37E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302Q07/10/19/37E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-318
3.145 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
Rev: 1.02e 5/2012
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology




GSI Technology

GS81302Q19GE Datasheet Preview

GS81302Q19GE Datasheet

144Mb SigmaQuad-II+ Burst of 2 SRAM

No Preview Available !

GS81302Q07/10/19/37E-318/300/250/200
16M x 8 SigmaQuad-II SRAM—Top View
123456789
A CQ SA SA W NW1 K SA R SA
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
NW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC D4 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D5
Q5
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS VDDQ
NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D7 NC VSS SA SA SA VSS NC
P NC NC Q7 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. B5 is the expansion address.
10
SA
NC
NC
NC
D2
NC
NC
VREF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
Rev: 1.02e 5/2012
2/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology


Part Number GS81302Q19GE
Description 144Mb SigmaQuad-II+ Burst of 2 SRAM
Maker GSI Technology
Total Page 28 Pages
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