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GS81302Q19GE - 144Mb SigmaQuad-II+ Burst of 2 SRAM

This page provides the datasheet information for the GS81302Q19GE, a member of the GS81302Q07E-318 144Mb SigmaQuad-II+ Burst of 2 SRAM family.

Datasheet Summary

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0 BW3 Synchronous Byte Writes Input Active Low NW0 NW1 Synchronous Nybble Writes Input Active Low (x8 onl

Features

  • 2.0 clock Latency.
  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully co.

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Datasheet preview – GS81302Q19GE

Datasheet Details

Part number GS81302Q19GE
Manufacturer GSI Technology
File Size 203.39 KB
Description 144Mb SigmaQuad-II+ Burst of 2 SRAM
Datasheet download datasheet GS81302Q19GE Datasheet
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Full PDF Text Transcription

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GS81302Q07/10/19/37E-318/300/250/200 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaQuad-II+TM Burst of 2 SRAM 318 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.
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