GSI Technology GS81302R36E
The GS81302R08/09/18/36E are built in compliance with the SigmaDDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302R08/09/18/36E SigmaDDR-II SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.| Part No. | GS81302R36E |
|---|---|
| Datasheet | GS81302R36E Download |
| Manufacturer |  GSI Technology |
| Description | 144Mb SigmaDDR-II Burst of 4 SRAM |
| Buy | Stock & Price |
FEATURES
● Simultaneous Read and Write SigmaDDR™ Interface● Common I/O bus
● JEDEC-standard pinout and package
● Double Data Rate interface
● Byte Write (x36 and x18) and Nybble Write (x8) function
● Burst of 4 Read and Write
● 1.8 V +100/–100 mV core power supply
● 1.5 V or 1.8 V HSTL Interface
● Pipelined read operation with self-timed Late Write
● Fully coherent read and write pipelines
● ZQ pin for programmable output drive strength
● IEEE 1149.1 JTAG-compliant Boundary Scan
● Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices
● 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
● RoHS-compliant 165-bump BGA package available SigmaDDR™ Family Overview They are 150,994,944-bit (144Mb) SRAMs. Clocking and Addressing Schemes The GS81302R08/09/18/36E SigmaDDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs.
