Datasheet Summary
GS81302T07/10/19/37E-450/400/350/333/300
165-Bump BGA mercial Temp Industrial Temp
144Mb SigmaDDRTM-II+ Burst of 2 SRAM
450 MHz- 300 MHz 1.8 V VDD
1.8 V or 1.5 V I/O
Features
- 2.0 Clock Latency
- Simultaneous Read and Write SigmaDDR™ Interface
- mon I/O bus
- JEDEC-standard pinout and package
- Double Data Rate interface
- Byte Write controls sampled at data-in time
- Burst of 2 Read and Write
- On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs
- 1.8 V +100/- 100 mV core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation with self-timed Late Write
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive...