Datasheet4U Logo Datasheet4U.com

GS81302T19E - 144Mb SigmaDDR-II+ Burst of 2 SRAM

Download the GS81302T19E datasheet PDF. This datasheet also covers the GS81302T107E-450 variant, as both devices belong to the same 144mb sigmaddr-ii+ burst of 2 sram family and are provided as variant models within a single manufacturer datasheet.

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R/W Synchronous Read Input High: Read Low: Write BW0 BW3 Synchronous Byte Writes Input Active Low LD Synchronous Load Pin Input Active Low K Input Clock Input Active High K Input Clock

Features

  • 2.0 Clock Latency.
  • Simultaneous Read and Write SigmaDDR™ Interface.
  • Common I/O bus.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 2 Read and Write.
  • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS81302T107E-450-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS81302T19E
Manufacturer GSI Technology
File Size 219.45 KB
Description 144Mb SigmaDDR-II+ Burst of 2 SRAM
Datasheet download datasheet GS81302T19E Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
GS810C Microprocessor Reset Monitors Vishay Siliconix
GS816118 (GS816118 - GS816136) Sync Burst SRAMs GSI
GS816118B (GS816118B - GS816136B) Sync Burst SRAMs GSI
GS816132 (GS816118 - GS816136) Sync Burst SRAMs GSI
GS816132B (GS816118B - GS816136B) Sync Burst SRAMs GSI

Other Datasheets by GSI Technology

Part Number Description
GS81302T19GE 144Mb SigmaDDR-II+ Burst of 2 SRAM
GS81302T107E 144Mb SigmaDDR-II+ Burst of 2 SRAM
GS81302T10E 144Mb SigmaDDR-II+ Burst of 2 SRAM
GS81302T10GE 144Mb SigmaDDR-II+ Burst of 2 SRAM
GS81302T110E 144Mb SigmaDDR-II+ Burst of 2 SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS81302T07/10/19/37E-450/400/350/333/300 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid pin (QVLD) Support • IEEE 1149.
Published: |