GS81302TT06E Datasheet | GSI Technology

GS81302TT06/11/20/38E-500/450/400/350 165-Bump BGA mercial Temp Industrial Temp 144Mb Sigma DDRTM-II+ Burst of 2 SRAM 500 MHz- 350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features - 2.5 Clock Latency - Simultaneous Read and Write Sigma DDRTM Interface - JEDEC-standard pinout and package - Double Data Rate interface - Byte Write controls sampled at data-in time - Burst of 2 Read and Write - Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs - 1.8 V +100/- 100 m V core power supply - 1.5 V or 1.8 V HSTL Interface - Pipelined read operation - Fully coherent read and write pipelines - ZQ pin for programmable output drive strength - Data Valid Pin (QVLD) Support - IEEE 1149.1 JTAG-pliant Boundary Scan - 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package - Ro HS-pliant 165-bump BGA package available Sigma DDR-II™ Family Overview The GS81302TT06/11/20/38E are built in pliance with the Sigma DDR-II+ SRAM pinout...