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GS81313LT36GK Datasheet PDF

GSI Technology GS81313LT36GK

The GS81313LT18/36GK SigmaDDR-IIIe ECCRAMs are synchronous devices. They employ three pairs of positive and negative input clocks; one pair of master clocks, CK and CK, and two pairs of write data clocks, KD[1:0] and KD[1:0].
Part No. GS81313LT36GK
Datasheet GS81313LT36GK Download
Manufacturer
GSI Technology
Description 144Mb SigmaDDR-IIIe Burst of 2 ECCRAM
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FEATURES

● 4Mb x 36 and 8Mb x 18 organizations available
● 833 MHz maximum operating frequency
● 833 MT/s peak transaction rate (in millions per second)
● 60 Gb/s peak data bandwidth (in x36 devices)
● Common I/O DDR Data Bus
● Non-multiplexed SDR Address Bus
● One operation - Read or Write - per clock cycle
● Burst of 2 Read and Write operations
● 3 cycle Read Latency
● On-chip ECC with virtually zero SER
● 1.25V ~ 1.3V core voltage
● 1.2V ~ 1.3V HSTL I/O interface
● Configurable ODT (on-die termination)
● ZQ pin for programmable driver impedance
● ZT pin for programmable ODT impedance
● IEEE 1149.1 JTAG-compliant Boundary Scan
● 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- compliant BGA package SigmaDDR-IIIe™ Family Overview SigmaDDR-IIIe ECCRAMs are the Common I/O half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance ECCRAMs. Although very similar to GSI's second generation of networking SRAMs (the SigmaQuad-II/SigmaDDR-II family), these third generation devices offer several new features that help enable significantly higher performance.
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