* Register-Register Late Write mode, Pipelined Read mode
* 2.5 V +200/
  –200 mV core power supply
* 1.5 V or 1.8 V HSTL Interface
* ZQ contr.

and in Flow Through mode NBT SRAMs. Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be w.

250 MHz
  –357 MHz 2.5 V VDD HSTL I/O Because GS815018/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initia.

GS815018AB-300

GS815018AB-333

GS815018AB-250

GS815036AB-250

GS815036AB-300

GS815036AB-333

GS815036AB-357

GS8150V18AB-250

GS8150V18AB-300

GS8150V18AB-333

GS8150V18AB-357

GS8150V36AB-250

GS8150V36AB-300

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