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GS816236D Datasheet Preview

GS816236D Datasheet

(GS816218x - GS816272c) Sync Burst SRAMs

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GS816236D pdf
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GS816218(B/D)/GS816236(B/D)/GS816272(C)
119-, 165-, & 209-Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 36, 256K x 72
18Mb Sync Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
Functional Description
Applications
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs,
the device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip set
support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is a SCD
(Single Cycle Deselect) and DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. DCD SRAMs pipeline disable
commands to the same degree as read commands. SCD SRAMs
pipeline deselect commands one stage less than read commands.
SCD RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers. DCD
RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816218(B/D)/GS816236(B/D)/GS816272(C) operates on
a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V
compatible. Separate output power (VDDQ) pins are used to
decouple output noise from the internal circuits and are 3.3 V and
2.5 V compatible.
Parameter Synopsis
Pipeline
3-1-1-1
3.3 V
Flow Through
2-1-1-1
3.3 V
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
-250
2.5
4.0
280
330
n/a
5.5
5.5
175
200
n/a
-225
2.7
4.4
255
300
n/a
6.0
6.0
165
190
n/a
-200
3.0
5.0
230
270
350
6.5
6.5
160
180
225
-166
3.4
6.0
200
230
300
7.0
7.0
150
170
115
-150
3.8
6.7
185
215
270
7.5
7.5
145
165
210
-133
4.0
7.5
165
190
245
8.5
8.5
135
150
185
Unit
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
Rev: 2.17 11/2004
1/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology



GSI Technology
GSI Technology

GS816236D Datasheet Preview

GS816236D Datasheet

(GS816218x - GS816272c) Sync Burst SRAMs

No Preview Available !

GS816236D pdf
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816272 Pad Out—209 Bump BGATop View (Package C)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Rev 10
1
DQG
DQG
DQG
DQG
DQPG
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPD
DQD
DQD
DQD
DQD
2
DQG
DQG
DQG
DQG
DQPC
DQC
DQC
DQC
DQC
NC
DQH
DQH
DQH
DQH
DQPH
DQD
DQD
DQD
DQD
3
A
BC
BH
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
CK
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
A
TMS
45678
E2
ADSP
ADSC
ADV
E3
BG NC BW A BB
BD NC E1 NC BE
NC NC G GW NC
VDDQ
VDD
VDD
VDD
VDDQ
VSS VSS ZQ VSS VSS
VDDQ
VDD
MCH
VDD
VDDQ
VSS VSS MCL VSS
VSS
VDDQ
VDD
MCL
VDD
VDDQ
NC VSS MCL VSS NC
VDDQ
VDD
FT
VDD
VDDQ
VSS VSS MCL VSS
VSS
VDDQ
VDD
SCD
VDD
VDDQ
VSS VSS ZZ VSS VSS
VDDQ
VDD
VDD
VDD
VDDQ
NC NC LBO NC NC
A1 A A1 A
A
A A A1 A A
TDI A A0 A TDO
11 x 19 Bump BGA14 x 22 mm2 Body1 mm Bump Pitch
9
A
BF
BA
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
A
TCK
10
DQB
DQB
DQB
DQB
DQP
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPA
DQE
DQE
DQE
DQE
11
DQB
DQB
DQB
DQB
DQPB
DQF
DQF
DQF
DQF
NC
DQA
DQA
DQA
DQA
DQPE
DQE
DQE
DQE
DQE
Rev: 2.17 11/2004
2/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology


Part Number GS816236D
Description (GS816218x - GS816272c) Sync Burst SRAMs
Maker GSI Technology
Total Page 30 Pages
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