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GS8170DW36AC-250 - (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM

This page provides the datasheet information for the GS8170DW36AC-250, a member of the GS8170DW36AC (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM family.

Description

Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Features

  • Double Late Write mode, Pipelined Read mode.
  • JEDEC-standard SigmaRAM™ pinout and package.
  • 1.8 V +150/.
  • 100 mV core power supply.
  • 1.8 V CMOS Interface.
  • ZQ controlled user-selectable output drive strength.
  • Dual Cycle Deselect.
  • Burst Read and Write option.
  • Fully coherent read and write pipelines.
  • Echo Clock outputs track data output drivers.
  • Byte write operation (9-bit bytes).
  • 2 user-programma.

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Datasheet preview – GS8170DW36AC-250

Datasheet Details

Part number GS8170DW36AC-250
Manufacturer GSI Technology
File Size 1.08 MB
Description (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM
Datasheet download datasheet GS8170DW36AC-250 Datasheet
Additional preview pages of the GS8170DW36AC-250 datasheet.

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Other Datasheets by GSI Technology
  • GS8170DW36AC-300 - (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM
  • GS8170DW36AC-333 - (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM
  • GS8170DW36AC-350 - (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM
  • GS8170DW36AC - (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM
  • GS8170DW36C - (GS8170DW36C / GS8170DW72C) Double Late Write SigmaRAM
  • GS8170DW36C-250 - (GS8170DW36C / GS8170DW72C) Double Late Write SigmaRAM
  • GS8170DW36C-300 - (GS8170DW36C / GS8170DW72C) Double Late Write SigmaRAM
  • GS8170DW36C-333 - (GS8170DW36C / GS8170DW72C) Double Late Write SigmaRAM

Full PDF Text Transcription

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GS8170DW36/72AC-350/333/300/250 209-Bump BGA Commercial Temp Industrial Temp Features • Double Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • Byte write operation (9-bit bytes) • 2 user-programmable chip enable inputs • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices • Pb-Free 209-bump BGA package available 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™ 250 MHz–350 MHz 1.8 V VDD 1.
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