* Double Late Write mode, Pipelined Read mode
* JEDEC-standard SigmaRAM™ pinout and package
* 1.8 V +150/
* 100 mV core power supply
* 1.8 V CMOS Interface
* ZQ controlled user-selectable output drive strength
* Dual Cycle Deselect
* Burs
GS8170DW72C-350 Datasheet (673.20 KB)
GS8170DW72C-350
GSI Technology
673.20 KB
(gs8170dw36c / gs8170dw72c) double late write sigmaram.
Preliminary GS8170DW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™ 200 MHz .
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