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GS8170LW72C-300 - (GS8170LW36C / GS8170LW72C) Late Write SigmaRAM

Download the GS8170LW72C-300 datasheet PDF. This datasheet also covers the GS8170LW36C variant, as both devices belong to the same (gs8170lw36c / gs8170lw72c) late write sigmaram family and are provided as variant models within a single manufacturer datasheet.

General Description

200 MHz

GS8170LW36/72 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs.

They are 18,874,368-bit (18Mb) SRAMs.

Key Features

  • Late Write mode, Pipelined Read mode.
  • JEDEC-standard SigmaRAM™ pinout and package.
  • 1.8 V +150/.
  • 100 mV core power supply.
  • 1.8 V CMOS Interface.
  • ZQ controlled user-selectable output drive strength.
  • Dual Cycle Deselect.
  • Burst Read and Write option.
  • Fully coherent read and write pipelines.
  • Echo Clock outputs track data output drivers.
  • Byte write operation (9-bit bytes).
  • 2 user-programmable chi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8170LW36C_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8170LW72C-300
Manufacturer GSI Technology
File Size 946.36 KB
Description (GS8170LW36C / GS8170LW72C) Late Write SigmaRAM
Datasheet download datasheet GS8170LW72C-300 Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8170LW72C-333 (GS8170LW36C / GS8170LW72C) Late Write SigmaRAM
GS8170LW72C-200 (GS8170LW36C / GS8170LW72C) Late Write SigmaRAM
GS8170LW72C-250 (GS8170LW36C / GS8170LW72C) Late Write SigmaRAM
GS8170LW72C (GS8170LW36C / GS8170LW72C) Late Write SigmaRAM
GS8170LW72AC (GS8170LW36AC / GS8170LW72AC) Late Write SigmaRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS8170LW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp Features • Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • Byte write operation (9-bit bytes) • 2 user-programmable chip enable inputs • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM™ Functional Description 200 MHz–333 MHz 1.8 V VDD 1.