GSI Technology GS8180QV18BD
The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. Each internal read and write operation in a SigmaQuad-II B2 RAM is two times wider than the device I/O bus.| Part No. | GS8180QV18BD |
|---|---|
| Datasheet | GS8180QV18BD Download |
| Manufacturer |  GSI Technology |
| Description | 18Mb Burst of 2 SigmaQuad SRAM |
| Buy | Stock & Price |
FEATURES
● Simultaneous Read and Write SigmaQuad™ Interface● JEDEC-standard pinout and package
● Dual DoubleData Rate interface
● Byte Write controls sampled at data-in time
● Burst of 2 Read and Write
● 2.5 V +100/–100 mV core power supply
● 1.5 V or 1.8 V HSTL Interface
● Pipelined read operation
● Fully coherent read and write pipelines
● ZQ mode pin for programmable output drive strength
● IEEE 1149.1 JTAG-compliant Boundary Scan
● Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
● RoHS-compliant 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package SigmaRAM™ Family Overview GS8180QV18/36B are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand.
