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GS8180QV36BD Datasheet Preview

GS8180QV36BD Datasheet

18Mb Burst of 2 SigmaQuad SRAM

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GS8180QV18/36BD-200/167
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Burst of 2
SigmaQuad SRAM
200 MHz–167 MHz
2.5 V VDD
1.8 V or 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual DoubleData Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 2.5 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
• RoHS-compliant 165-bump, 13 mm x 15 mm, 1 mm bump
pitch BGA package
SigmaRAMFamily Overview
GS8180QV18/36B are built in compliance with the
SigmaQuad SRAM pinout standard for Separate I/O
synchronous SRAMs. They are18,874,368-bit (18Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
family of SigmaRAMs, the SigmaQuad family of SRAMs
allows a user to implement the interface protocol best suited to
the task at hand.
Clocking and Addressing Schemes
A Burst of 2 SigmaQuad SRAM is a synchronous device. It
employs two input register clock inputs, K and K. K and K are
independent single-ended clock inputs, not differential inputs
to a single differential clock input buffer. The device also
allows the user to manipulate the output register clock inputs
quasi independently with the C and C clock inputs. C and C are
also independent single-ended clock inputs, not differential
inputs. If the C clocks are tied high, the K clocks are routed
internally to fire the output registers instead.
Each internal read and write operation in a SigmaQuad-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II B2 RAM is always one address pin less than the
advertised index depth (e.g., the 2M x 8 has a 1M addressable
index).
SigmaQuad SRAMs are offered in a number of configurations.
Some emulate and enhance other synchronous separate I/O
SRAMs. A higher performance SDR (Single Data Rate) Burst
of 2 version is also offered. The logical differences between
the protocols employed by these RAMs hinge mainly on
various combinations of address bursting, output data
registering, and write cueing. Along with the Common I/O
Parameter Synopsis*
tKHKH
tKHQV
-200
5.0 ns
2.3 ns
-167
6.0 ns
2.5 ns
Rev: 1.02b 11/2011
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology




GSI Technology

GS8180QV36BD Datasheet Preview

GS8180QV36BD Datasheet

18Mb Burst of 2 SigmaQuad SRAM

No Preview Available !

GS8180QV18/36BD-200/167
1M x 18 SigmaQuad SRAM—Top View (Package D)
1 2 3 4 5 6 7 8 9 10
A
NC
MCL/SA NC/SA
(144Mb) (36Mb)
W
BW1
K
NC
R
SA
MCL/SA
(72Mb)
B NC Q9 D9 SA NC K BW0 SA NC NC
C NC NC D10 VSS SA SA SA VSS NC Q7
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
D6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD VDDQ NC
NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD VDDQ NC
NC
H
NC
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
Q4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
NC
M NC NC D16 VSS VSS VSS VSS VSS NC Q1
N NC D17 Q16 VSS SA SA SA VSS NC NC
P NC NC Q17 SA SA C SA SA NC D0
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. MCL = Must Connect Low
4. It is recommended that H1 be tied low for compatibility with future devices.
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.02b 11/2011
2/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology


Part Number GS8180QV36BD
Description 18Mb Burst of 2 SigmaQuad SRAM
Maker GSI Technology
Total Page 28 Pages
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