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GS8182T09BGD Datasheet PDF

GSI Technology GS8182T09BGD

The GS8182T08/09/18/36BD are built in compliance with the SigmaDDR-II SRAM pinout stand
Part No. GS8182T09BGD
Datasheet GS8182T09BGD Download
Manufacturer
GSI Technology
Description 18Mb SigmaDDR-II Burst of 2 SRAM
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GS8182T09BGD datasheet page 1 preview

FEATURES

● Simultaneous Read and Write SigmaDDR-II™ Interface
● Common I/O bus
● JEDEC-standard pinout and package
● Double Data Rate interface
● Byte Write (x36 and x18) and Nybble Write (x8) function
● Burst of 2 Read and Write
● 1.8 V +100/–100 mV core power supply
● 1.5 V or 1.8 V HSTL Interface
● Pipelined read operation with self-timed Late Write
● Fully coherent read and write pipelines
● ZQ pin for programmable output drive strength
● IEEE 1149.1 JTAG-compliant Boundary Scan
● Pin-compatible with present 9Mb, 36Mb, and 72Mb and future 144Mb devices
● 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
● RoHS-compliant 165-bump BGA package available SigmaDDR-II™ Family Overview
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